The invention is generally directed to plating bath and surface treatment compositions for forming thin films in electronic devices, such as semiconductor and other solid state devices.
Much research and design focus has been to scale electronic devices to very small dimensions. However to ultimately take advantage of such small scaling, higher performance interconnects are required. To date, aluminum has been the metal used to create such interconnects and bus lines as in liquid crystal displays (LCDs). But with the scaling of interconnects, cross sectional area, line resistance and current density capacity are a limiting factor of total chip performance. Additionally for some applications like LCD bus lines, aluminum does not have adequate conductivity as displays get larger. To overcome these limitations, industry is moving away from Al towards use of copper, which has a resistivity of 1.72μ cm, approximately ⅔ of pure Al or almost half of Al/0.5% Cu. Copper also has an increased current density threshold, which ultimately may make use of copper as interconnects more reliable and able to handle higher currents.
Copper, however, is not compatible with the subtractive etch processes that are traditionally used in forming Al interconnects. Therefore, a process known as a dual damascene approach is used with both copper and aluminum, where a via is etched, followed or preceded by etching of a trench, allowing for creation of both trenches and vias in the same dielectric layer. Both structures are then filled with Cu, and then the resultant structure is polished using chemical mechanical polishing, resulting in an inlaid Cu interconnect.
However, the process of filling the trenches with copper is not a simple single step. Because copper readily migrates into the surrounding dielectric, such as SiO2, barrier layers such as TaN are deposited before the addition of Cu. The Cu is then deposited on the barrier layer in a two step process, starting with a seed layer step followed by a subsequent enhancement step, either by electroplating or vapor deposition. This seed layer's characteristics play an important role in the overall structure of the resultant film. A strongly textured seed layer is important in forming an overall surface that is smooth and has large grains in the overall film. The texture, or orientation distribution of polycrystalline materials, can affect the physical properties of the metal film, and as such, the (111) texture in copper films is generally preferred over (200) texture due to increased electromigration times. With the proper barrier and seed layers, the grains of electroplated copper films in trenches are quite large and a near-bamboo structure can be obtained. This desirable microstructure enhances the reliability of damascene copper interconnects. Fine grain sizes often also degrade electromigration times, which typically occur with chemical vapor deposition processes of the film rather than electroplating process.
Despite their advantages, there are difficulties in implementing copper interconnects. For example, the copper interconnects are affected by electromigration, i.e., movement of copper under an electric potential gradient. Barrier layers in vias and trenches, underneath the copper layer, have been used to prevent copper electromigration and can also be used to improve copper adhesion to the dielectric material. More recently, a barrier layer deposited on top of the copper filled trench, referred to as a cap layer, is used to prevent copper migration at the interface between the top of the copper layer in a trench and the next dielectric layer. See Hu et al., RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 42nd Annual (2004 IEEE International); Kohn et al., JOURNAL OF APPLIED PHYSICS 92(9):5508-5511 (2002). One approach to forming this capping layer is to deposit a thin layer of the appropriate cap material on the entire wafer followed by a patterning step to remove the cap material from the dielectric surface. Electroless plating has also been used to form cap layers.
Today, there is no cost effective means of depositing a lower resistance metal such as copper. In the semiconductor interconnect application, seed layers are created by atomic layer deposition which is expensive and has inadequate coverage of high aspect ratio vias.
In addition, there is currently no cost effective means of forming a cap layer using a deposition and patterning technique, and the use of electroless plating suffers from a number of shortcomings. For example, limited selectivity and instability of the electroless deposition bath make the use of electroless plating for forming cap layers less than ideal.